The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly not impliedly admitted as prior art against the present disclosure.
The present disclosure relates to memory systems and methods, and more specifically memory interface systems.
During development of a particular circuit design, a Field Programmable Gate Array (FPGA) may be used to emulate the behavior of the circuit design as it would be implemented on an Application-Specific Integrated Circuit (ASIC). By emulating the behavior of the circuit design, the FPGA may be used to facilitate testing of circuit design prototypes. However, an FPGA typically operates at a clock rate that is substantially less than the clock rate of the ASIC. The slower clock rate of the FPGA may present problems when the emulated circuit interfaces with memory circuitry, and the emulation requires full cycle accuracy (i.e., an exact correspondence at each clock cycle between the states of the components of the circuit design as emulated on an FPGA and the states of the components of the circuit design as they would be implemented on an ASIC). In particular, because the clock rate of the FPGA may fall below the minimum operating frequency of the memory circuitry, a modification of the circuit design or a modification of the memory circuitry may be required for the emulated circuit design to properly interface with the memory circuitry.